Extended Abstract WC2 pp.497-500 of Fifth International Conference on Indium Phosphide and Related Materials, held at Paris in France from 19th to 22nd Apr. 1993, discloses a prior art HEMT (high electron mobility transistor) shown in FIG. 12(a). FIG. 12(a) is a cross-sectional view illustrating the prior art HEMT structure with an n type InAlAs carrier supply layer on an InP substrate and with a Schottky forming layer on the n type InAlAs carrier supply layer. FIG. 12(b) is a diagram for explaining thermal degradation of the electrical characteristics of the HEMT.
In FIG. 12(a), reference numeral 101 designates a semi-insulating (hereinafter referred to as S.I.) InP substrate, numeral 102 designates an undoped InP layer having a thickness of about 10 nm, numeral 103 designates an undoped InGaAs channel layer having a thickness of about 20 nm, numeral 104 designates an undoped InAlAs spacer layer having a thickness of about 3 nm, numeral 105 designates an n.sup.+ type InAlAs electron supply layer having a thickness of about 15 nm and a dopant concentration of 3.times.10.sup.18 cm.sup.-3, numeral 106 designates a Schottky forming layer comprising such as undoped In.sub.0.75 Ga.sub.0.25 P and having a thickness of about 10 nm, numeral 107 designates an n.sup.+ type InGaAs ohmic layer having a thickness of about 20 nm and a dopant concentration of 5.times.10.sup.18 cm.sup.-3, numeral 108 designates a source electrode, numeral 109 designates a drain electrode, and numeral 110 designates a gate electrode.
In FIG. 12(b), the abscissa shows an annealing temperature (unit: .degree.C.), and the ordinate shows a sheet carrier concentration (unit: 10.sup.12 cm.sup.-2) of two-dimensional electron gas produced in the interface of the undoped InGaAs channel layer 103 at the side of the undoped InAlAs spacer layer 104. Circles, triangles and squares shown in the figure represent the cases where materials of the Schottky forming layer 106 are In.sub.0.75 Ga.sub.0.25 P, InP and InAlAs, respectively.
A description is given of the thermal degradation of the electrical characteristics of the HEMT. In the above-described literature, in order to investigate thermal stability of the HEMT shown in FIG. 12(a), Fujita, et al., the authors, prepared the same structures as the main structure of the HEMT shown in FIG. 12(a). Three kinds of semiconductor laminated structures were obtained by successively laminating the undoped InP layer 102, the undoped InGaAs channel layer 103, the undoped InAlAs spacer layer 104 and the n.sup.+ type InAlAs electron supply layer 105 on the S.I. InP substrate 101, and subsequently laminating the Schottky forming layers 106 respectively comprising In.sub.0.75 Ga.sub.0.25 P, InP and InAlAs. These laminated structures were annealed at 300.degree. C. or 350.degree. C. for five minutes in an ambient of nitrogen, and measurements of sheet carrier concentrations of the two-dimensional electron gas produced in the interface of the undoped InGaAs channel layer 103 at the side of the undoped InAlAs spacer layer 104 were conducted for the respective laminated structures. The results are as illustrated in FIG. 12(b). As is known from the figure, regardless of the materials of the electrode layers 106, In.sub.0.75 Ga.sub.0.25 P, InP and InAlAs, the sheet carrier concentrations decreased by annealing at 300.degree. C. or higher.
These results indicate that, when an HEMT is annealed at 300.degree. C. or higher, the electrical characteristics of the HEMT are thermally degraded and a desired sheet carrier concentration of the two-dimensional electron gas is not obtained, so that there occur problems, such as an increase in resistance of a region where the two-dimensional electron gas is produced, failing to obtain expected HEMT characteristics. Concerning this phenomenon, Fujita, et al. reported that the decrease in surface sheet carrier concentration could be attributed to an increase in surface depletion layer caused by surface deterioration of the InAlAs layer.
Meanwhile, the inventors of the present invention have studied the thermal degradation of the electrical characteristics of the HEMT, as described in Applied Physics Letters Volume 66 No.7 pp.863-865. FIG. 13 is a cross-sectional view illustrating a semiconductor laminated structure used for the studies, and FIG. 14 is a graph showing the results obtained from the studies. In FIG. 13, reference numeral 111 designates an S.I. InP substrate, numeral 112 designates an intrinsic (hereinafter referred to as i-) AlInAs buffer layer having a thickness of 2500 .ANG., numeral 113 designates an i-GaInAs channel layer having a thickness of 500 .ANG., and numeral 114 designates an AlInAs electron supply layer having a thickness of 340 .ANG.. The i-GaInAs channel layer 113 includes a two-dimensional electron gas layer 116 in the vicinity of the interface at the side of the AlInAs electron supply layer 114, and the AlInAs electron supply layer 114 includes a spacer layer 115, i.e., a layer portion where an Si planar doping is performed to a height of 20 .ANG. from the interface with the i-GaInAs channel layer 113.
In FIG. 14, the abscissa shows an annealing temperature (unit: .degree.C.), and the ordinate shows a relationship between sheet carrier concentration N.sub.s0 of a two-dimensional electron gas layer before annealing and sheet carrier concentration N.sub.s thereof after annealing, i.e., N.sub.s /N.sub.s0.
The studies were carried out as follows. The semiconductor laminated structure similar to the HEMT structure shown in FIG. 13, with the AlIAs electron supply layer 114 planar-doped with Si on the i-GaInAs channel layer 113, was annealed at different temperatures for fifteen minutes in the nitrogen ambient. Then, the sheet carrier concentrations of the two-dimensional electron gas layer 116 formed in the vicinity of the interface of the i-GaInAs channel layer 113 at the side of the AlInAs electron supply layer 114 were measured by Hall effect measurements. As shown in FIG. 14, also in the above-described semiconductor laminated structure, the sheet carrier concentration decreases by annealing, which implies that an HEMT with its electrical characteristics degraded is fabricated by including an annealing process.
FIG. 15 is a cross-sectional view illustrating a semiconductor laminated structure used in studies for identifying the causes of the thermal degradation of the electrical characteristics of the prior art semiconductor device. In the figure, reference numeral 21 designates an S.I. InP substrate, numeral 22 designates an i-AlInAs layer having a thickness of about 4000 .ANG., and numeral 23 designates an AlInAs layer doped with Si as a dopant impurity and having a thickness of about 1300 .ANG..
The semiconductor laminated structures as shown in FIG. 15 were respectively formed in an MBE (molecular beam epitaxy) chamber by successively laminating the i-AlInAs layers 22 and the Si planar-doped AlInAs layers 23 on the S.I. InP substrates 21. After taking the semiconductor laminated structures out from the growth chamber, annealing was conducted for the laminated structures at temperatures of 300.degree. C., 400.degree. C., and 450.degree. C. for fifteen minutes under the nitrogen ambient, respectively. Then, impurity species of the semiconductor laminated structures were measured by secondary ion mass spectroscopy (SIMS) measurement. The results of the impurity measurements are as illustrated in FIG. 16.
In FIG. 16, the abscissa shows a depth of the semiconductor laminated structure from its surface (unit: .mu.m), and the ordinate shows a fluorine concentration (unit: cm.sup.-3). White circles shown in the figure represent a fluorine profile for the as-grown semiconductor laminated structure, white squares represent a fluorine profile for the laminated structure that was annealed at 300.degree. C., white triangles represent a fluorine profile for the laminated structure that was annealed at 400.degree. C., and black squares represent a fluorine profile for the laminated structure that was annealed at 450.degree. C.
The following facts were found by the above-described studies. .sup.19 F (fluorine) was diffused into the semiconductor laminated structure by annealing, which was based on the results obtained by checking the whole mass of impurities and detecting the mass number 19 by SIMS measurement; the amount of .sup.19 F increases as annealing temperature increases; .sup.19 F was dominantly involved in the Si-doped layer; and .sup.19 F was also accumulated at the interface between the epitaxial layers and the substrate.
From these facts, it is found out that fluorine (.sup.19 F) diffuses into the semiconductor laminated structure during annealing, which has not ever been known. Because no fluorine was detected for other materials, except for the Si-doped AlInAs layer 23, it is reasonably thought that the fluorine diffusion is a phenomenon peculiar to the AlInAs layer 23 doped with a dopant impurity, such as Si. In addition, when the origin of fluorine was investigated, it was found that no fluorine was used in the growth chamber of MBE or MOCVD which was used for the growth of the semiconductor laminated structure and that no fluorine was actively supplied in the laboratory. However, fluorine of about 0.3 atomic % was detected by analyzing the surface of the Si-doped AlInAs layer 23 just after the growth by electron spectroscopy for chemical analysis (ESCA). From these results, it is concluded that a small amount of fluorine, produced from hydrogen fluoride (HF) used for the semiconductor fabricating processes, remains in the air in the laboratory, and the fluorine in the air is attracted to and absorbed on the surface of the Si-doped AlInAs layer 23 when its surface is exposed to the air, resulting in the diffusion into the AlInAs layer 23.
Further, changes on standing in respective profiles (not shown) before and after annealing were investigated for elements such as Si and nitrogen, except for fluorine, and the respective profiles before and after annealing were almost the same.
As described above, the fluorine in the air diffuses into the Si-doped AlInAs layer 23 by annealing, and the profiles of the other elements do not change by annealing. Consequently, this phenomenon, i.e., the fluorine adsorption and diffusion by annealing, is thought to cause the thermal degradation of the electrical characteristics of the semiconductor device.
In order to avoid the degradation due to the fluorine diffusion, the fluorine remaining in the air may be completely removed. However, generally, in a plant where semiconductor fabrication is performed, the fluorine in the air remains without being completely removed, and complete removal of the fluorine is very difficult. Therefore, it is difficult to avoid fluorine diffusion.
Consequently, as long as the fluorine diffuses by annealing from the surface of the AlInAs layer doped with a dopant impurity, such as Si, which surface is exposed to the air, it is impossible to avoid the thermal degradation of a semiconductor device including a AlInAs layer doped with a dopant impurity.
In addition, it was ascertained that the thermal degradation occurred by retaining a lower temperature than the annealing temperatures used for the above-described studies, for a long time. FIG. 17 is a graph showing a relationship between carrier concentration of the Si-doped AlInAs layer 23 and time of retaining the temperature when the semiconductor laminated structure shown in FIG. 15 was annealed at 200.degree. C. In the figure, the ordinate shows a carrier concentration (unit: cm.sup.-3), and the abscissa shows time of retaining a temperature (hr). As is known from FIG. 17, the carrier concentration is decreased when the retaining time exceeds 100 hours at a low temperature of 200.degree. C. This indicates that the thermal degradation of the semiconductor device occurs even at such a low temperature, and that the semiconductor device may be thermally degraded in the long term, even at a further low temperature, so that reliability of the semiconductor device is very low.
As described above, in a prior art semiconductor device including an AlInAs layer doped with a dopant impurity, like an HEMT, when thermal treatment is performed under an ambient including a carrier gas, such as nitrogen and hydrogen, degradation of the electrical characteristics, such as a decrease in sheet carrier concentration, occurs. Usually, in order to confirm reliability of a semiconductor device, the semiconductor device is operated at a high temperature, which is likely to degrade the semiconductor characteristics, thereby confirming changes of the characteristics on standing. In the prior art semiconductor device, however, because the sheet carrier concentration decreases in a reliability test including the thermal treatment, the obtained results are not satisfactory, failing to produce a semiconductor device having high reliability.
In addition, since the characteristics are thermally degraded as described above, it is very difficult to operate the prior art semiconductor device at a high temperature for a long time, while maintaining desired characteristics, which makes it difficult to provide a semiconductor device having high reliability in high-temperature operation.
Further, in a prior art method of fabricating a semiconductor device, when the fabricating method requires a thermal treating process at a high temperature after forming an AlInAs layer doped with a dopant impurity, the electrical characteristics of the AlInAs layer doped with a dopant impurity are thermally degraded, so that a semiconductor device having desired characteristics is not fabricated. For example, in an HEMT including the AlInAs layer doped with a dopant impurity as a carrier supply layer, the sheet carrier concentration of two-dimensional electron gas decreases due to the thermal degradation, so that desired operating characteristics are not obtained.